module top_module (
    input clk,
    input [2:0] y,
    input x,
    output Y0,
    output z
);

    `define STT_W 3
    `define STT_W1 `STT_W - 1

    wire [`STT_W1:0]   state = y;
    reg [`STT_W1:0]   nxt_state;

    localparam IDLE  = `STT_W'd0;
    localparam s_1   = `STT_W'd1;
    localparam s_10  = `STT_W'd2;
    localparam s_11  = `STT_W'd3;
    localparam s_100 = `STT_W'd4;

    // State transition logic (combinational)
    always @(*) begin
        case (state)
            IDLE:begin
                if(x)
                    nxt_state = s_1;
                else
                    nxt_state = IDLE;
            end
            s_1:begin
                if(x)
                    nxt_state = s_100;
                else
                    nxt_state = s_1;
            end
            s_10:begin
                if(x)
                    nxt_state = s_1;
                else
                    nxt_state = s_10;
            end
            s_11:begin
                if(x)
                    nxt_state = s_10;
                else
                    nxt_state = s_1;
            end
            s_100:begin
                if(x)
                    nxt_state =s_100;
                else
                    nxt_state = s_11;
            end
          default: begin
            nxt_state = IDLE;
          end
        endcase
    end
    
    assign  Y0   =   nxt_state[0];
    assign  z    =   state >= s_11;

endmodule
